1. Field of the Invention
This invention relates to the field of operational amplifiers (op amps), and particularly to the op amp output stages.
2. Description of the Related Art
An op amp typically includes an input stage which produces a differential current in response to the application of a differential input voltage, and an output stage which produces a single-ended or differential output which varies with the differential current. An example is shown in FIG. 1. The input stage 10 comprises PMOS transistors MP1 and MP2, and a tail current source 12. A differential input voltage is applied across the gates of MP1 and MP2, and a differential current is produced at their drain terminals in response.
The differential current is connected to a gain stage 14xe2x80x94typically comprising a number of transistors connected in a folded-cascode configuration (biased with bias voltages Vb3, Vb4, and Vb5)xe2x80x94which drives an output stage 15. The output stage in FIG. 1 is arranged in what is sometimes called a xe2x80x9cMonticelli architecturexe2x80x9d, described, for example, in Monticelli, xe2x80x9cA Quad CMOS Single-Supply Op Amp with Rail-to-Rail Output Swing,xe2x80x9d Journal of Solid-State Circuits, December 1986, pp. 1026-1034, which features a current switch 16 that drives a pair of output transistors MP3 and MN1 connected in a back-to-back common-source configuration. The op amp""s output Vo is taken at the junction 17 of MP3 and MN1. The current switch comprises an NMOS transistor MN2 and a PMOS transistor MP4, which receive respective bias voltages Vb1 and Vb2 and are connected between a pair of nodes 18 and 20. Nodes 18 and 20 are connected to receive the differential current from gain stage 14. When properly biased, MN2 and MP4 conduct equal currents when the differential current is zero. The voltages developed at nodes 18 and 20 drive output transistors MP3 and MN1, respectively. Output stage 15 typically includes a frequency compensation scheme. One of many possible schemes is shown in FIG. 1, with a first compensation capacitor Cl connected between node 18 and junction 17, and a second compensation capacitor C2 connected between node 20 and junction 17.
This circuit arrangement suffers from a number of drawbacks, however. The gate capacitances of output transistors MP3 and MN1 can affect the dominant pole in the op amp""s frequency response, which can make the amplifier""s bandwidth dependent on the output transistors used. The gate capacitances can also lower the frequency of the op amp""s secondary pole, which establishes the bandwidth""s upper limit. These problems can be particularly troublesome when the output transistors are external field-effect transistors (FETs), which typically have higher gate capacitances.
An op amp output stage is presented which overcomes the problems noted above. The adverse affects of gate capacitance on the amplifier""s dynamic performance are mitigated, and other benefits are realized as well.
The present invention includes a pair of buffer amplifiers which are interposed between the current switch and the output transistors in a Monticelli-based output stage. The buffer amps act to buffer the output transistors"" gate capacitance, thereby allowing the output transistors to be any desired size without adversely affecting the op amp""s dynamic performance. This enables the op amp""s compensation capacitors to set the amplifier""s bandwidth. It also moves the secondary pole to a higher frequency. The buffer amplifiers can also provide gain, which effectively multiplies the transconductance of the output transistors and further extends out the secondary pole location.
In addition, the buffer amplifiers can be used to provide level translation between the current switch and the output transistors, which can provide additional headroom for the amplifier""s gain stage.